A constant goal of integrated circuit (“IC”) designers is to minimize the size of individual features within ICs so as to improve the device density of the overall system. Typically, a standard cell library of macros for individual features is used to lay out the IC, with various layout design rules being applied to regulate the interactions among the macros. All standard cell libraries are created using the same published design rules. However, the public design rules applicable to standard cells are not applied to memory bit cells, which are hand-crafted to be as small as possible.
As a result of the requirements imposed on standard cell libraries due to the necessity to adhere to design rules, many ICs are not designed to be as small as they may otherwise be designed without the rules. It is desired to minimize IC designs, thereby increasing the number of ICs that can be fabricated from a single wafer.